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hdmi transceiver data sheet adv7622 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no respon sibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 an alog devices, inc. all rights reserved. technical support www.analog.com features 4 - input, 1 - output multiplexed hdmi? transceiver high - bandwidth digital content protection (hdcp 1.4) hdcp repeater support 225 mhz hdmi rx and tx support 36 - /30 - /24 - bit deep color supports dvi rgb graphics up to 1600 1200 at 60 hz ultralow jitt er digital pll (100% deskew) quad hdmi rx input format details available on all unselected ports adaptive equalizer for cable lengths up to 30 meters internal extended display identification data ( edid ) ram edid replication (512 bytes per port) edid with h dmi cable 5 v power support 5 v detect inputs hot plug assertion control pins single hdmi tx output edid data extraction hot plug detect (hpd) input audio support hdmi - compatible audio interface dedicated flexible audio input/output port s/pdif (iec 6 0 9 58- compatible) digital audio input/ output super audio cd ( sacd ) with dsd input/ output interface high bit rate (hbr) audio dolby? truehd dts - hd master audio? full audio input and output support general interrupt controller with 3 interrupt outputs stdi (standa rd identification circuit ) software libraries, driver , and application available 2 - layer pcb design supported applications avr s htib sound bar with hdmi repeater support h br enabled tvs other repeater applications general description the adv 7622 is a h igh performance, four - input, one - output, high - definition multimedia interface (hdmi) transc eiver that integrates hdmi receiver and transmitter functions with digital audio i/os onto one chip. it supports all hdcp repeater functions through fully tested ana log devices, inc., repeater software libraries and drivers. the adv 7622 supports all mandatory hdmi 3d tv formats in addition to all hdtv formats up to 1080p , 36 - bit deep color. the adv 7622 a lso features an integrated hdmi cec controller that supports capa bility , discovery , and control (cdc). the adv 7622 offers a dedicated flexible audio output port and a dedicated audio input port to allow for easy extraction and insertion of audio data into and out of the hdmi stream. hdmi audio f ormats, including sacd vi a dsd and compressed high bit rate audio via hbr, are supported. the adv 7622 also features an audio return channel (arc) receiver. arc simplifies cabling by combining upstream audio capability in a conventional hdmi cable. fabricated in an advanced cmos p rocess, the adv 7622 is provided in a 144 - lead, 20 mm 20 mm , pb - free lqfp an d is specified over the 0c to 70c temperature range.
adv7622 data sheet rev. d | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 digital, hdmi, and ac specifications ...................................... 4 data and i 2 c timing characteristics ......................................... 5 power specifications .................................................................... 7 absolute maximum ratings ............................................................ 8 package thermal performance ................................................... 8 esd caution...................................................................................8 pin configuration and function descriptions ..............................9 functional overview ...................................................................... 13 hdmi receiver ........................................................................... 13 hdmi transmitter ..................................................................... 13 i 2 c interface ................................................................................ 13 other features ............................................................................ 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 7/13rev. spc to rev. d: limited to open market release
data sheet adv7622 rev. d | page 3 of 16 functional block dia gram ch0 ch1 ch2 video data de vs hs audio data video data de vs hs audio data video data de vs hs audio data video data de vs hs audio data 08727-001 xtal xtal1 rxa_c rxb_c rxc_c rxd_c rxa_0 rxa_1 rxa_2 video/audio clock generation rx pll 5v_deta cec 5v_detb 5v_detc 5v_detd txc tx0 tx1 tx2 5v detect component processor scl sdata alsb cs i 2 c controller pwrdn reset global controls ddca_sda ddca_scl ddcb_sda ddcb_scl ddcc_sda ddcc_scl ddcd_sda ddcd_scl ap0_in ap1_in ap2_in ap3_in ap4_in ap5_in sclk_in mclk_in ap0_out ap1_out ap2_out ap3_out ap4_out ap5_out sclk_out mclk_out arc+ rx edid/ repeater controller hp_ctrla hp_ctrlb hp_ctrlc hp_ctrld rx hpd controller ep_miso ep_mosi ep_cs ep_sck spi master/ slave equalizer rxb_0 rxb_1 rxb_2 equalizer sampler sampler rxc_0 rxc_1 rxc_2 equalizer sampler rxd_0 rxd_1 rxd_2 equalizer cec controller edid ram sampler hdmi receiver processor transmitter packet builder hdcp encryption engine hdmi encoder serializer tmds drivers int1 int2 int_tx interrupt controller txddc_sda txddc_scl tx edid/hdcp controller edid/hdcp buffer hpd_arc? tx hpd controller hdcp decryption engine sync measurement packet processor infoframe packet memory audio processor arc receiver audio capture hdcp keys tx pll adv7622 figure 1.
adv7622 data sheet rev. d | page 4 of 16 specifications cvdd = 1.8 v 5%, dvdd = 1.8 v 5%, dvddio = 3.3 v 5%, pvdd = 1.8 v 5%, tvdd = 3.3 v 5%, txavdd = 1.8 v 5%, txpvdd = 1.8 v 5%, txplvdd = 1.8 v 5%, t min to t max = 0 c to 70c. digital, hdmi, and a c specifications table 1 . parameter test conditions /comments min typ max unit digital inputs input high voltage (v ih ) 2 v input low voltage (v il ) 0.8 v input current (i in ) reset , ep_m iso , alsb , and cs pi n s ?60 +60 a other digital inputs ?10 +10 a input capacitance (c in ) 10 pf digital inputs (5 v tolerant) 1 input high voltage (v ih ) 2.6 v input low voltage (v il ) 0.8 v input current (i in ) ?82 +82 a digital outputs output high voltage (v oh ) 2.4 v output low voltage (v ol ) 0.4 v high impedance leakage current (i leak ) 10 a output capacitance (c out ) 20 pf hdmi tmds differential pin capacitance 0.3 pf ac specifications input specifications intra pair (+ to ?) differential input skew for tmds clock rates up to 222.75 mhz 0.4 t bit ps intrapair (+ to ?) differential input skew for tmds clock rates above 222.75 mhz 0.15 t bit + 112 ps channel - to - channel differential input skew 0.2 t pixel + 1 .78 ns tmds input clock range 25 225 mhz tmds input clock jitter tolerance 0.5 0.25 t bit output specifications tmds output clock frequency 20 225 mhz tmds output clock duty cycle 48 52 % tmds output differential swing 900 1100 1200 mv differential output timing low -to - high transition time 75 175 ps high - to - low transition time 75 175 ps 1 the following pins are 5 v tolerant: ddca_scl, ddca_sda, ddcb_scl, ddcb_sda, ddcc_scl, ddcc_sda, ddcd_scl, ddcd_sda, txddc_sd a, txddc_scl, hp_ctrla, hp_ctrlb, hp_ctrlc, hp_ctrld, hpd_arc?, 5v_deta, 5v_detb, 5v_detc, 5v_detd, pwrdn , cec, arc+.
data sheet adv7622 rev. d | page 5 of 16 data and i 2 c timing characteris tics table 2 . parameter symbol test conditions /comments min typ max unit vi deo system clock and xtal crystal nominal frequency 28.6363 6 mhz crystal frequency stability 5 0 ppm external clock source 1 external crystal must operate at 1.8 v input high voltage v ih xtal driven with external clock source 1.2 v input low voltage v il xtal driven with external clock source 0.4 v reset feature reset pulse width 5 ms i 2 c ports (fast mode) xcl frequency 2 400 khz xcl mini mum pulse width high 2 t 1 600 ns xcl minimum pulse width low 2 t 2 1.3 s hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns xda setup time 2 t 5 100 ns xcl and xda rise time 2 t 6 300 ns xcl and xda fall time 2 t 7 300 ns setup time (stop condition) t 8 0.6 s i 2 c ports (normal mode) xcl frequency 2 100 khz x c l minimum pulse width high 2 t 1 4.0 s xcl minimum pulse width low 2 t 2 4.7 s hold time (start condition) t 3 4.0 s setup time (start condition) t 4 4.7 s xda setup tim e 2 t 5 250 ns xcl and xda rise time 2 t 6 1000 ns xcl and xda fall time 2 t 7 300 ns setup time (stop condition) t 8 4.0 s audio output port (master mode) sclk mark space ratio t 13 :t 14 45:55 55:45 % duty cycle lrclk data transition time (ap5_out ) t 15 end of valid data to negative sclk edge 10 ns lrclk data transition time ( ap5_out ) t 16 negative sclk edge to start of valid data 10 ns i 2 s data transition time ( apx_out ) 3 t 17 end of valid data to negative sclk edge 5 ns i 2 s data transition time ( apx_out ) 3 t 18 negative sclk edge to start of valid data 5 ns audio input port i 2 s data set up time ( apx_in ) 3 t 19 2 ns i 2 s hold time ( apx_in ) 3 t 20 2 ns lrclk setup time ( ap5_in ) t 19 2 ns lrclk hold time ( ap5_in ) t 2 0 2 ns 1 this part must be configure d for external oscillator operation . a 1.8 v oscillator must be used. 2 the prefix x refers to s, ddca_s, ddcb_s, ddcc_s, and ddcd_s. 3 the suffix x refers to 0, 1, 2, 3, 4 , and 5 .
adv7622 data sheet rev. d | page 6 of 16 timing diagrams xda xcl t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 t 3 notes 1. x refers to s, ddca_s, ddcb_s, ddcc_s, ddcd_s. 08727-002 figure 2. i 2 c timing sclk lrclk i2s[3:0] left-justified mode i2s[3:0] right-justified mode i2s[3:0] i 2 s mode msb msb ? 1 t 13 t 14 t 15 t 17 t 18 t 16 msb msb ? 1 lsb msb t 17 t 18 t 17 t 18 0 8727-004 figure 3. i 2 s output timing valid data valid data i2s[3:0], lrclk sclk rising edge r0x0b[6] = 0 sclk falling edge r0x0b[6] = 1 i2s[3:0] lrclk t 19 t 20 t 19 t 20 08727-007 figure 4. i 2 s input timing
data sheet adv7622 rev. d | page 7 of 16 power specifications table 3 . parameter min typ max unit test conditions/comment s power supplies comparator power supply (cvdd) 1.71 1.8 1.89 v digital core power supply (dvdd) 1.71 1.8 1.89 v digital i/o power supply (dvddio) 3.14 3.3 3.46 v pll power supply (pvdd) 1.71 1.8 1.89 v termination power supply (tvdd) 3.14 3 .3 3.46 v tx tmds output power supply (txavdd) 1.71 1.8 1.89 v tx power supply (txpvdd) 1.71 1.8 1.89 v tx pll power supply (txplvdd) 1.71 1.8 1.89 v current consumption 1 , 2 , 3 , 4 comparator power supply (i cvdd ) 126 143 ma four ports with 10 80p 12 - bit 1.0 ma power - down mode 1 1.0 ma power - down mode 0 digital core power supply (i dvdd ) 167 195 ma four ports with 1080p 12 - bit 9.0 ma power - down mode 1 6.7 ma power - down mode 0 digital i/o power supply (i dvddio ) 1.0 2.0 ma four ports with 1080p 12 - bit 3.4 ma power - down mode 1 3.3 ma power - down mode 0 pll power supply (i pvdd ) 33.7 39.4 ma four ports with 1080p 12 - bit 1.7 ma power - down mode 1 1.6 ma power - down mode 0 termination power supply (i tvdd ) 206 227 ma f our ports with 1080p 12 - bit 0.4 ma power - down mode 1 0.4 ma power - down mode 0 tx tmds output power supply (i txavdd ) 21.7 25.2 ma four ports with 1080p 12 - bit 0.5 ma power - down mode 1 0.3 ma power - down mode 0 tx power supply (i txpvdd ) 6. 02 6.97 ma four ports with 1080p 12 - bit 2.8 ma power - down mode 1 2.8 ma power - down mode 0 tx pll power supply (i txplvdd ) 23.2 26.5 ma four ports with 1080p 12 - bit 1.6 ma power - down mode 1 1.6 ma power - down mode 0 1 all maximum current values are guaran teed by characterization to assist in power supply design. 2 typical current consumption values are recorded with nominal voltage supply levels and at room temperature . 3 maximum current consumption values are recorded with maximum rated voltage supply le vels and a t room temperature . 4 termination power supply includes tvdd current consumed off chip.
adv7622 data sheet rev. d | page 8 of 16 absolute maximum ratings table 4. parameter rating cvdd to gnd 2.2 v dvdd to gnd 2.2 v pvdd to gnd 2.2 v dvddio to gnd 4.0 v tvdd to gnd 4.0 v txavdd to gnd 2.2 v txpvdd to gnd 2.2 v txplvdd to gnd 2.2 v digital inputs voltage to gnd gnd ? 0.3 v to dvddio + 0.3 v up to a maximum of 4.0 v 5 v tolerant digital inputs to gnd 1 5.5 v digital output voltage to gnd gnd ? 0.3 v to dvddio + 0.3 v up to a maximum of 4.0 v xtal, xtal1 pins ?0.3 v to pvdd to +0.3 v maximum junction temperature (t j max ) 125c storage temperature 150c infrared reflow, soldering (20 sec) 260c 1 the following inputs are 3.3 v inpu ts but are 5 v tolerant: ddca_scl, ddca_sda, ddcb_scl, ddcb_sda, ddcc_scl, ddcc_sda, ddcd_scl, ddcd_sda, txddc_sda, txddc_scl, hp_ctrla, hp_ctrlb, hp_ctrlc, hp_ctrld, hpd_arc?, 5v_deta, 5v_detb, 5v_detc, 5v_detd, pwrdn , cec, arc+. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal performance to reduce power consumption when using the adv7622, turn off the unused sections of the part. due to printed circuit board (pcb) metal variation and, thus, variation in pcb heat conductivity, the value of ja may differ for various pcbs. the most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature because this eliminates the variance associated with the ja value. the maximum junction temperature (t j max ) of 125c must not be exceeded. the following equation calculates the junction temperature using the measured package surface temperature and applies only when no heat sink is used on the dut: t j = t s + ( jt w total ) where: t s = the package surface temperature (c). jt = 0.6c/w for a 144-ball lqfp. w total = ((cvdd i cvdd ) + (dvdd i dvdd ) + (pvdd i pvdd ) + (dvddio i dvddio ) + (0.7 tvdd i tvdd ) + (txavdd i txavdd ) + (txpvdd i txpvdd ) + (txplvdd i txplvdd )) note that for w total , 5% of tvdd power is dissipated on the part itself. esd caution
data sheet adv7622 rev. d | page 9 of 16 pin configuration and function description s adv7622 t o p view (not to scale) pin 1 08727-005 1 ddcc_sc l 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 73 dvddio 74 ap3_in 75 ap2_in 76 ap1_in 77 ap0_in 78 sd at a 79 sc l 80 dgnd 81 dvdd 82 int1 83 int2 84 int_tx 85 dgndio 86 dvddio 87 ap0_out 88 ap1_out 89 ap2_out 90 ap3_out 91 ap4_out 92 dgnd 93 dvdd 94 ap5_out 95 sclk_out 96 mclk_out 97 reset 98 pwrdn 99 pgnd 100 pvdd 101 x t a l 102 x t al1 103 pvdd 104 pgnd 105 hp_ctrl a 106 5v_de t a 107 rterm 108 ddca_sd a 109 1 10 11 1 1 12 1 13 1 14 1 15 1 16 1 17 1 18 1 19 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 ddcc_sd a 37 txp l vdd 38 txgnd 39 txpgnd 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 ext_swing hpd_arc? arc+ txddc_sda txddc_scl txavdd txgnd txc? txc+ txgnd tx0? tx0+ txgnd tx1? tx1+ txavdd tx2? tx2+ txgnd cec dgnd dvdd alsb cs ep_sck ep_cs ep_mosi ep_miso mclk_in sclk_in ap5_in ap4_in dgndio 5v_detc hp_ctrlc rxb_2+ rxb_2? tvdd rxb_1+ rxb_1? cgnd rxb_0+ rxb_0? tvdd rxb_c+ rxb_c? cgnd cvdd ddcb_scl ddcb_sda dvdd dgnd 5v_detb hp_ctrlb rxa_2+ rxa_2? tvdd rxa_1+ rxa_1? cgnd rxa_0+ rxa_0? tvdd rxa_c+ rxa_c? cgnd cvdd ddca_scl cvdd cgnd rxc_c? rxc_c+ tvdd rxc_0? rxc_0+ cgnd rxc_1? rxc_1+ tvdd rxc_2? rxc_2+ hp_ctrld 5v_detd dgnd dvdd ddcd_sda ddcd_scl cvdd cgnd rxd_c? rxd_c+ tvdd rxd_0? rxd_0+ cgnd rxd_1? rxd_1+ tvdd rxd_2? rxd_2+ cvdd cgnd txpvdd figure 5. pin configuration table 5 . pin function descriptions pin no. mnemonic type description 1 ddcc_scl digital i nput hdcp slave serial clock port c. ddcc_scl is a 3.3 v input that is 5 v tolerant. 2 cvdd power receiver comparator supply voltage (1.8 v) . 3 cgnd ground tvd d and cvdd ground . 4 rxc_c ? hdmi i nput digital input clock complement of p ort c in the hdmi i nterface. 5 rxc_c+ hdmi i nput digital input clock true of p ort c in the hdmi i nterface. 6 tvdd power receiver terminator supply voltage (3.3 v) . 7 rxc_0 ? hdmi i nput digital input channel 0 complement of p ort c in the hdmi i nterface. 8 rxc_0+ hdmi i nput digital input channel 0 true of p ort c in the hdmi i nterface. 9 cgnd ground tvdd and cvdd ground . 10 rxc_1 ? hdmi i nput digital input c hannel 1 complement of p o rt c in the hdmi i nterface. 11 rxc_1+ hdmi i nput digital input c hannel 1 true of p ort c in the hdmi i nterface. 12 tvdd power receiver terminator supply voltage (3.3 v) .
adv7622 data sheet rev. d | page 10 of 16 pin no. mnemonic type description 13 rxc_2 ? hdmi i nput digital input channel 2 complement of p ort c in the hdmi i nterf ace. 14 rxc_2+ hdmi i nput digital input channel 2 true of p ort c in the hdmi i nterface. 15 hp_ctrld digital o utput hot plug detect for port d. 16 5v_detd digital i nput 5 v detect p in for p ort d in the hdmi i nterface. 17 dgnd ground dvdd ground . 18 dvd d power digital supply voltage (1.8 v) . 19 ddcd_sda digital i/o hdcp slave serial data port d. ddcd_sda is a 3.3 v input/output that is 5 v tolerant. 20 ddcd_scl digital i nput hdcp slave serial clock port d. ddcd_scl is a 3.3 v input that is 5 v tolerant . 21 cvdd power receiver comparator supply voltage (1.8 v) . 22 cgnd ground tvdd and cvdd ground . 23 rxd_c ? hdmi i nput digital input c lock complement of p ort d in the hdmi i nterface. 24 rxd_c+ hdmi i nput digital input clock true of p ort d in the hdmi i n terface. 25 tvdd power receiver terminator supply voltage (3.3 v) . 26 rxd_0 ? hdmi i nput digital input channel 0 complement of p ort d in the hdmi i nterface. 27 rxd_0+ hdmi i nput digital input channel 0 true of p ort d in the hdmi i nterface. 28 cgnd groun d tvdd and cvdd ground . 29 rxd_1 ? hdmi i nput digital input channel 1 c omplement of p ort d in the hdmi i nterface. 30 rxd_1+ hdmi i nput digital input channel 1 t rue of p ort d in the hdmi i nterface. 31 tvdd power receiver terminator supply voltage (3.3 v) . 32 rxd_2 ? hdmi i nput digital input channel 2 c omplement of p ort d in the hdmi i nterface. 33 rxd_2+ hdmi i nput digital input channel 2 t rue of p ort d in the hdmi i nterface. 34 cvdd power receiver comparator supply voltage (1.8 v) . 35 cgnd ground tvdd a nd cvdd ground . 36 txpvdd power 1.8 v power supply for digital and i/o power supply. th is pin suppl ies power to the digital logic and i/os. it should be filtered and as quiet as possible. 37 txplvdd power 1.8 v power supply. 38 txgnd ground txpvdd groun d . 39 txpgnd ground txplvdd ground . 40 ext_swing analog i nput this pin s ets the internal reference currents . place a n 887 resistor (1% tolerance) between this pin and ground. 41 hpd_arc? analog input hot plug detect signal and audio return channel inverted input. this pin indicates to the interface whether the receiver is connected. 42 arc+ analog input audio return channel (arc) input (5 v tolerant). 43 txddc_sda digital i/o serial port data i/o to receiver. this pin serves as the master to the ddc bus. it supports a 5 v cmos logic level. 44 txddc_scl digital output serial port data clock to receiver. this pin ser ves as the master clock for the ddc bus. it supports a 5 v cmos logic level. 45 txavdd power 1.8 v power supply for tmds outputs. 46 txgnd ground txavdd ground. 47 txc? hdmi output differential clock output. differential clock output at the tmds clock rate; supports tmds logic level. 48 txc+ hdmi output differential clock output. differential clock output at the tmds clock rate; supports tmds logic level. 49 txgnd ground txavdd ground. 50 tx0? hdmi output differential output channel 0 complement. differential output of the red data at 10 the pixel clock rate; supports tmds logic level. 51 tx0+ hdmi output differential output channel 0 true. differential output o f the red data at 10 the pixel clock rate; supports tmds logic level. 52 txgnd ground txavdd ground. 53 tx1? hdmi output differential output channel 1 complement. differential output of the red data at 10 the pixel clock rate; supports tmds logic lev el. 54 tx1+ hdmi output differential output channel 1 true. differential output of the red data at 10 the pixel clock rate; supports tmds logic level. 55 txavdd power 1.8 v power supply for tmds outputs.
data sheet adv7622 rev. d | page 11 of 16 pin no. mnemonic type description 56 tx2? hdmi output differential output channel 2 complement. differential output of the red data at 10 the pixel clock rate; supports tmds logic level. 57 tx2+ hdmi output differential output channel 2 true. differential output of the red data at 10 the pixel clock rate; supports tmds logic level. 58 txgnd ground txavdd ground. 59 cec digital i/o consumer electronics control channel (5 v tolerant). 60 dgnd ground dvdd ground. 61 dvdd power digital supply voltage (1.8 v). 62 alsb digital input this pin is used to set the i 2 c address of the rx i o and the tx main map. 63 cs digital input chip select pin. this pin must be set low or left floating for the chip to process i 2 c messages that are destined for the adv7622. the adv7622 ignores i 2 c messages that it receives if this pin is high. 64 ep_sck digital output spi clock interface for the edid. 65 ep_cs digital output spi chip selected interface for the edid. 66 ep_mosi digital output spi master out/slave in for the edid. 67 ep_miso digital input spi master in/slave out for t he edid. 68 mclk_in digital input audio reference clock. 128 n f s with n = 1, 2, 3, or 4. set to 128 sampling frequency (f s ), 256 f s , 384 f s , or 512 f s . it supports cmos logic levels from 1.8 v to 3.3 v. 69 sclk_in digital input i 2 s audio clo ck. it supports cmos logic levels from 1.8 v to 3.3 v. 70 ap5_in digital input audio input port 5. it supports cmos logic levels from 1.8 v to 3.3 v. 71 ap4_in digital input audio input port 4. it supports cmos logic levels from 1.8 v to 3.3 v. 72 dgndi o ground dvddio ground. 73 dvddio power digital i/o supply voltage (3.3 v). 74 ap3_in digital input audio input port 3. it supports cmos logic levels from 1.8 v to 3.3 v. 75 ap2_in digital input audio input port 2. it supports cmos logic levels from 1.8 v to 3.3 v. 76 ap1_in digital input audio input port 1. it supports cmos logic levels from 1.8 v to 3.3 v. 77 ap0_in digital input audio input port 0. it supports cmos logic levels from 1.8 v to 3.3 v. 78 sdata digital i/o i 2 c port serial data input/ou tput pin. sdata is the data line for the control port. 79 scl digital input i 2 c port serial clock input. scl is the clock line for the control port. 80 dgnd ground dvdd ground. 81 dvdd power digital supply voltage (1.8 v). 82 int1 (amute1) digital outp ut interrupt pin. this pin can be active low or active high. when status bits change, this pin is triggered. the events that trigger an interrupt are under user control. this pin can also output an audio mute signal. 83 int2 (amute2) digital output inter rupt pin. this pin can be active low or active high. when status bits change, this pin is triggered. the events that trigger an interrupt are under user control. this pin can also output an audio mute signal. 84 int_tx digital output interrupt; open dra in. a 2 k pull - up resistor to the microcontroller i/o supply is recommended. 85 dgndio ground dvddio ground. 86 dvddio power digital i/o supply voltage (3.3 v). 87 ap0_out digital output audio output port 0. 88 ap1_out digital output audio output port 1 . 89 ap2_out digital output audio output port 2. 90 ap3_out digital output audio output port 3. 91 ap4_out digital output audio output port 4. 92 dgnd ground ground for dvdd. 93 dvdd power digital supply voltage (1.8 v). 94 ap5_out digital out put audio output port 5. 95 sclk_out digital output audio serial clock output. 96 mclk_out digital output audio master clock output. 97 reset digital input system reset input. active low. a minimum low reset pulse width of 5 ms is requ ired to reset the adv7622 circuitry. 98 pwrdn digital input active low power - down pin. if used, this pin should be pulled high to power up the adv7622. this pin can also be used as an in - system power detect where internal edid can be po wered from a 5 v signal of the hdmi port when it is connected to active equipment.
adv7622 data sheet rev. d | page 12 of 16 pin no. mnemonic type description 99 pgnd ground pvdd ground. 100 pvdd power pll supply voltage (1.8 v). 101 x tal miscellaneous analog input pin for 28.63636 mhz crystal or an external 1.8 v 28.63636 mh z clock oscillator source to clock the adv7622. 102 x tal1 miscellaneous analog crystal output pin. this pin should be left floating if a clock oscillator is used. 103 pvdd power pll supply voltage (1.8 v). 104 pgnd ground pvdd ground. 105 hp_ctrla digital output hot plug detect for port a. 106 5v_deta digital input 5 v detect pin for port a in the hdmi interface. 107 rterm miscellaneous analog this pin sets the internal termination resistance. a 500 resistor between this pin and ground should be used. 108 ddca_sda digital i/o hdcp slave serial data port a. ddca_sda is a 3.3 v input/output that is 5 v tolerant. 109 ddca_scl digital input hdcp slave serial clo ck port a. ddca_scl is a 3.3 v input that is 5 v tolerant. 110 cvdd power receiver comparator supply voltage (1.8 v). 111 cgnd ground tvdd and cvdd ground. 112 rxa_c? hdmi input digital input clock complement of port a in the hdmi interface. 113 rxa_c+ hdmi input digital input clock true of port a in the hdmi interface. 114 tvdd power receiver terminator supply voltage (3.3 v). 115 rxa_0? hdmi input digital input channel 0 complement of port a in the hdmi interface. 116 rxa_0+ hdmi input digital inpu t channel 0 true of port a in the hdmi interface. 117 cgnd ground tvdd and cvdd ground. 118 rxa_1? hdmi input digital input channel 1 complement of port a in the hdmi interface. 119 rxa_1+ hdmi input digital input channel 1 true of port a in the hdmi in terface. 120 tvdd power receiver terminator supply voltage (3.3 v). 121 rxa_2? hdmi input digital input channel 2 complement of port a in the hdmi interface. 122 rxa_2+ hdmi input digital input channel 2 true of port a in the hdmi interface. 123 hp_ctr lb digital output hot plug detect for port b. 124 5v_detb digital input 5 v detect pin for port b in the hdmi interface. 125 dgnd ground dvdd ground. 126 dvdd power digital supply voltage (1.8 v). 127 ddcb_sda digital i/o hdcp slave serial data port b. ddcb_sda is a 3.3 v input/output that is 5 v tolerant. 128 ddcb_scl digital input hdcp slave serial clock port b. ddcb_scl is a 3.3 v input that is 5 v tolerant. 129 cvdd power receiver comparator supply voltage (1.8 v). 130 cgnd ground tvdd and cvdd g round. 131 rxb_c? hdmi input digital input clock complement of port b in the hdmi interface. 132 rxb_c+ hdmi input digital input clock true of port b in the hdmi interface. 133 tvdd power receiver terminator supply voltage (3.3 v). 134 rxb_0? hdmi inpu t digital input channel 0 complement of port b in the hdmi interface. 135 rxb_0+ hdmi input digital input channel 0 true of port b in the hdmi interface. 136 cgnd ground tvdd and cvdd ground. 137 rxb_1? hdmi input digital input channel 1 complement of p ort b in the hdmi interface. 138 rxb_1+ hdmi input digital input channel 1 true of port b in the hdmi interface. 139 tvdd power receiver terminator supply voltage (3.3 v). 140 rxb_2? hdmi input digital input channel 2 complement of port b in the hdmi in terface. 141 rxb_2+ hdmi input digital input channel 2 true of port b in the hdmi interface. 142 hp_ctrlc digital output hot plug detect for port c. 143 5v_detc digital input 5 v detect pin for port c in the hdmi interface. 144 ddcc_sda digital i/o hdc p slave serial data port c. ddcc_sda is a 3.3 v input/output that is 5 v tolerant.
data sheet adv7622 rev. d | page 13 of 16 f unctional overview hdmi receiver the adv 7622 front end incorporates a 4:1 multiplexed hdmi rec eiver boasting support for hdmi features including 3d tv, content type bits , and advanced features , such as capability discovery and control. building on the feature set of existing analog devices hdmi devices, the adv 7622 also offers support for all hdtv formats up to 36- bit, 1080p deep color and all display resolutions up to ux ga (1600 1200 at 60 hz). with the inclusion of hdcp 1.4, displays can receive encrypted video content. the hdmi interface of the adv 7622 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the hdcp 1.4 protocol. repeater support is also offered by the adv 7622. the hdmi receiver offers advanced audio functionality. it supports multichannel i 2 s audio for up to eight channels. it also supports a 6 - dsd channel interface with each channel carrying an over - sampled 1 - bit representation of the audio signal as delivered on sacd. the adv 7622 can also receive hbr audio packet streams and output them through the hbr interface in an s / pdif format conformi ng to the iec 60958 standard. s / pdif is supported via the hpd back channel. the receiver also contains an audio mute controller, which can detect a variety of conditions that may result in audible extraneous noise in the audio output. on detection of these conditions, the audio data can be ramped to prevent audio clicks or pops. the adv 7622 hdmi receiver incorporates active, programmable equalization of the hdmi data signals that compensates for the high frequency losses inherent in hdmi and dvi cabling, especially at longer lengths and higher frequencies. the receiver also contains a programmable data island packet interrupt generator. hdmi transmitter the adv 7622 features a single hdmi transmitter supporting arc, 3d tv formats as well as all hdtv for mats up to 1080p, 36- bit deep color. supporting both single - ended and differential modes , the arc feature simplifies cabling by combining an upstream audio capability in a conventional hdmi cable. the transmitter features an on - chip mpu with an i 2 c maste r to perform hdcp operations and edid reading operations. i 2 c interface the adv 7622 supports a 2 - wire serial (i 2 c - compatible) microprocessor bus driving multiple peripherals. the adv 7622 is controlled by an external i 2 c master device, such as a microcont roller. other features other features include the following: ? fully qualified software low level libraries, driver , and application ? complete input and output audio support ? programmable interrupt request output pins: int 1 , int2, and int_tx ? chip select ? low p ower consumption: 1.8 v digital core, 1.8 v analog , and 3.3 v digital input/output, low power power - down mode, and green pc mode ? temperature range: 0c to 70c ? 20 mm 20 mm , pb - free, 144 - lead lqfp for more detailed product information about the adv 7622, c ontact your local analog devices sales office .
adv7622 data sheet rev. d | page 14 of 16 outline dimensions compliant to jedec standards ms-026-bfb 051706-a 0.27 0.22 0.17 1 36 37 73 72 108 144 109 top view (pins down) 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 22.20 22.00 sq 21.80 20.20 20.00 sq 19.80 figure 6. 144-lead low profile quad flat package [lqfp] (st-144) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADV7622BSTZ 0c to 70c 144-lead low profile quad flat package [lqfp] st-144 ADV7622BSTZ-rl 0c to 70c 144-lead low pr ofile quad flat package [lqfp] st-144 eval-adv7622eb1z evaluation board 1 z = rohs compliant part.
data sheet adv7622 rev. d | page 1 5 of 16 notes
adv7622 data sheet rev. d | page 16 of 16 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). hdmi, the hdmi logo, and high - definition multimedia interface are trademarks or registered trademarks of hdmi licensing llc in the unite d states and other countries. ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08727 - 0 - 7/13(d)

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